1. Field of the Invention
The invention relates to an adhesion assisting agent-bearing metal foil, a printed wiring board, and a production method of the printed wiring board. The invention also relates to a multilayer circuit board, a semiconductor chip-mounting substrate, and a semiconductor package substrate.
2. Description of the Related Art
Recently, electronic appliances have been required to be compact, lightweight and high speed, and high densification of printed wiring boards has advanced and in these years, therefore, production of a printed wiring board by a semi-additive method using electroplating has been drawing attention.
As a semi-additive method, Japanese Patent Application Laid-Open (JP-A) No. 10-4254 (application date: Jun. 14, 1996) discloses a method involving forming holes to be IVH in the resin surface in which a circuit is to be formed by laser; surface-roughening the resin surface with several μm by chemical roughening or plasma treatment; supplying a Pd catalyst; carrying out electroless plating in about 1 μm-thickness, forming a resist layer for pattern-wise electroplating, carrying out wiring formation by pattern-wise electroplating, and then removing the resist and power supply layer existing in the portion other than the circuit. According to this method, finer wiring formation is made possible as compared with a subtractive method with a high side etching degree. Further, JP-A No. 2003-158364 (application date: Nov. 22, 2001) discloses a separable metal foil with a thickness of 5 μm or thinner formed on a supporting metal foil. The method disclosed therein makes it possible to thin down the thickness of the metal foil. According to this method, since there is no need to carry out electroless plating on the surface of an insulating resin layer, a printed wiring board with a greater reliability can be produced.
However, according to these methods, the roughened shape adversely interferes with the fine wiring formation and also the electric properties are undesirably deteriorated due to the roughened shape.
JP-A No. 7-221444 (application date: Jan. 31, 1994) discloses a method involving forming a copper layer with about 1 μm thickness on one face of a polyimide film by using an electron beam evaporation apparatus and laminating the layer on an inner layer circuit through an adhesive or a prepreg to form an electric power supply layer. Also, JP-A No. 6-302965 . (application date: Apr. 16, 1993) discloses a method of forming an electric power supply layer on a dielectric layer by sputtering. It is possible to significantly lessen the degree of the roughened shape by forming the electric power supply layer by a dry process such as evaporation and sputtering, disclosed methods as compared with the conventional methods.
However, if the resin is made smooth in those methods, it becomes difficult to form a resin layer thereon. In other words, it becomes difficult to form a built-up layer on a core substrate or to form a solder resist on a substrate. Especially, if the insulating layer surface roughness Rz is 2.0 μm or less, the resin layer formation thereon becomes very hard, although it depends on the insulating layer. Even if laminating seems to be done, the substrate is very poor in resistance to moisture absorption and heat resistance in many cases. Particularly, in these years, low dielectric resin layers having no functional group have been used frequently for insulating layers and such a tendency has been more significant.
As described, wiring boards with an excellent fine wiring formation and electric properties and advantageous in terms of the production cost and having a high reliability and high frequency have not been made available so far.